1. Field of the Invention
This present invention relates generally to high-speed data converters, and more particularly to a high-speed parallel-to-serial CMOS data converter having a D flip-flop Matrix structure that can selectively convert a plurality of predetermined bit widths simply by adjusting the frequency of a loading clock.
2. Description of the Prior Art
The parallel-to-serial data converter is an important functional structure in many data transmitters. Basically, it latches the parallel input words and converts those words into a serial data sequence, precisely timed via a transmitting clock. For most applications, especially high-speed data links such as fibre channel and Gigabit Ethernet, a differential data stream is preferred since it helps to improve signal-to-noise (S/N) ratio, depress noise caused by switching drivers, and minimizes cross-talk.
Various parallel-to-serial data converter structures and associated methods of control have been suggested at one time or another, but in each instance, these structures leave something to be desired. For example, there is a need for an inexpensive parallel-to-serial data converter, i.e. using CMOS technology, that is capable of efficiently and reliably operating at Gigabit speeds and that allows a plurality of desired bit widths to be processed without requiring modifications to the existing converter structure. Converters are available that are suitable for use at Gigabit speeds, but generally such converters have been available only with expensive technologies such as GsAs or silicon bipolar.
One conventional implementation of a parallel-to-serial converter suitable for performing such a conversion includes a chain of D flip-flops that operate via a shift scheme such as disclosed in U.S. Pat. No. 5,654,707, issued Aug. 5, 1997 to Matsumoto entitled Parallel-To-Serial Data Conversion Circuit; U.S. Pat. No. 5 5,379,038, issued Jan. 3, 1995 to Matsumoto entitled Parallel-Serial Data Converter; and U.S. Pat. No. 5,247,652, issued Sep. 21, 1993 to Uda entitled Parallel To Serial Converter Enabling Operation At A High Bit Rate With Slow Components By Latching Sets Of Pulses Following Sequential Delays Equal To Clock Period. However, the aforesaid shift scheme has inherently unavoidable drawbacks that include: 1) All the D flip-flops in the chain work at the full data rate; hence the dynamic power dissipation is considerably large according to the high-speed data transition; 2) The single bit clock must necessarily drive all the D flip-flops, in which case the load is very large and brings difficulties for designing the clock driver; 3) The VCO generating the bit clock has to work at the data rate frequency, which is not easy to achieve at Gigabit levels; and 4) High-speed flip-flops are absolutely necessary to achieve a satisfactorily workable configuration which further challenges the final design. In consideration of the foregoing, it is not preferable to use a pure shift scheme in Gigabit applications.
An alternative implementation to the aforesaid shift scheme includes a selection scheme wherein all of the D flip-flops are put in parallel, with a switch added at each output port. Generally, a bus connects the outputs of the switches together to serialize the output data. Such configurations can extend to multi-levels, creating a tree-like data path. The selection scheme requires more clock signals and more complicated logic support than that required of shift schemes, but has benefits that include: 1) The D flip-flops will work at the much lower parallel data rate and the constrains for its design can be loosened; 2) The VCO need not work at the serial data rate which also eases the design constraints; and 3) Each switch is driven by a single clock phase so that the total load is distributed equally to the multi-phase clocks. However, a purely selection scheme will require many clock phases for a wide word, necessitating use of a VCO comprising many stages. Additionally, multi-phase clocks are not flexible for use with variable bit widths because the phase number necessarily must equal the word bit width.
Thus, prior known selection and shift conversion schemes taken individually are not suitable to accommodate high data rate parallel-to-serial conversion. In view of the above, a need exists in the art for an inexpensive parallel-to-serial converter having a simple clock architecture that is capable of efficiently and reliably converting data words of selectable bit widths at high bit rates.